FIG. 4 shows a conventional memory device 100, which in this example has arranged four memory banks 101a, 101b, 101c and 101d. The individual memory banks 101a–101d are connected to a comparison and compression circuit V arranged in an evaluation circuit region A. The comparison and data compression circuit V serves for testing the functionality of the individual memory banks 101a–101d of the memory module 100. It should be pointed out that the circuit arrangement illustrated in FIG. 4 is a detail from an arbitrary semiconductor memory chip with memory array and data path. It is disadvantageous that in the conventional memory module 100 only ever one memory bank 101a, 101b, 101c, or 101d at a time can transmit results onto a data bus D.
As shown below with reference to FIG. 5, the data bus comprises four data lines 103a–103d in this example of a conventional memory module. In a conventional manner, the memory banks 101a–101d in each case comprise secondary sense amplifiers 102a–102d. All data lines are connected to the comparison and data compression circuit in order to be able to perform a data comparison and a data compression.
FIG. 5 shows the memory module 100 illustrated schematically in FIG. 4 in greater detail. FIG. 5 shows only two memory banks 101a, 101b with the corresponding secondary sense amplifiers 102a–102d. It should be pointed out that only four sense amplifiers 102a–102d are shown by way of example here, whereas in principle a large number of secondary sense amplifiers 102a–102n is provided in a memory bank 101a–101n, where the number n may be greater than 100.
The requirement for increasingly higher storage densities gives rise to the problem that a chip area, i.e. a space requirement for the memory module, has to be reduced. In the case of the conventional memory modules illustrated in FIGS. 4 and 5, it is thus inexpedient that the comparison and data compression circuit identified by a reference symbol V is arranged in the evaluation circuit region A (dashed region in FIG. 4). The comparison and data compression circuit V serves for testing the individual memory banks 101a–101n of the memory module, it being disadvantageous that only one memory bank 101a–101d in each case can be tested at a specific time. It is disadvantageous that a simultaneous testing of the memory banks 101a–101n contained in the memory module 100 is not made possible, in such a way that the test time is increased (four-fold in the example shown in FIG. 4 in order to test all four memory banks).
This inexpediently leads to the disadvantage that the test costs are increased as a result of a lengthening of the test time when testing the conventional memory module 100 for functionality. An increase in parallelism when testing the memory module 100 could be provided by increasing the number of internal data lines 103a–103d. However, increasing data lines in this way inexpediently leads to the disadvantage that they cause a considerable space requirement, as a result of which the chip area is disadvantageously enlarged.